This invention relates to electronic devices, and more specifically to semiconductor memory integrated circuits and methods of fabrication.
The density of circuit elements increases as integrated circuits become more complex. In addition, more complex circuits are typically designed to operate at higher frequencies. As a result of the shrinking dimensions and increased speeds, undesirable capacitive coupling between circuit elements becomes a problem that must be addressed. Capacitive coupling is a particular problem in dynamic random access memories (DRAMs) as increasingly large amounts of memory capacity is placed on an integrated circuit. In particular, the bitlines of DRAMs are being placed closer in proximity to one another as the area available on the integrated circuit substrate is used more efficiently. The bitline-to-bitline coupling that results from such close spacing can caused data errors in the memory, and hence is a problem that must be addressed.
As the memory capacity of DRAMs has increased, designers have begun to use the vertical dimension as one approach to putting more capability in a given die space. In particular, the storage capacitors for DRAMs are typically formed away from the substrate surface, and with shapes designed to enhance the area, and hence capacitance, of the structure. A typical capacitor in use is the so-called crown cell. One problem with the vertical nature of these circuits is the large difference in height between the memory cell array and the peripheral circuits. The capacitors in the cell array can extend hundreds of nanometers above the surrounding periphery circuits. This height difference makes the patterning and etching of narrow and closely-spaced lines and vias in both the cell array and the periphery difficult.
In accordance with a preferred embodiment of the invention, there is disclosed an integrated circuit. The circuit includes a memory cell array, circuits peripheral to the array, and a conductor coupling the array to the peripheral circuits. The conductor has a first thickness in the array and a second thickness in the peripheral circuits.
In accordance with another preferred embodiment of the invention, there is disclosed an integrated circuit. The circuit includes a memory cell array including wordlines formed on a substrate and bitlines and capacitors formed over the wordlines. The bitlines have a first thickness and pitch. The circuit also includes circuits peripheral to the array including transistors formed in the substrate and conductors over the transistors. The conductors have a second thickness and pitch. The circuit is further characterized in that the bitlines and conductors are formed in a common conductive layer. In further embodiments, the first thickness and pitch are smaller than the second thickness and pitch.
An advantage of the inventive concepts is that the bitline and first conductor layers may be formed simultaneously, and yet may be produced in the thicknesses appropriate for use in both the cell array and periphery of a memory integrated circuit. A relatively thin bitline reduces line-to-line coupling, while a relatively thick periphery circuit interconnect provides low resistance. In one embodiment in accordance with the invention, the bitline/first-metal layer compensates for the height difference in the cell array and periphery by being relatively thin the cell array and relatively thick in the periphery.